1. Field of the Invention
This invention relates to a semiconductor device and a fabrication method thereof, and more particularly to a method for forming a titanium silicide film which is low in electric resist layerance and excellent in heat resist layerance, and a semiconductor device, such as a salicide CMOS transistor, which is reduced in junction leakage currents and suppressed in short-channel effect for raising drive power, and a method of fabricating the same.
2. Related Art
In insulated-gate field effect transistors employed in semiconductor integrated circuits currently available, there is reduction of depletion-layer electric charges carried by a gate electrode relative to the total amount of depletion-layer electric charges, as the device miniaturizes. As a result, the transistor is apt to cause short-channel effects involving lowering of threshold voltage, punch-through, and degradation in sub-threshold characteristics. One factor of such phenomenon is attributable to deep junctions of source and drain regions.
To suppress the short-channel effect, there arises a necessity of making junctions of source and drain regions shallower in commensurate with miniaturization of the device. In PMOS semiconductor devices, there is a general tendency of adopting a surface-channel transistor provided with p-type doping, because the conventional buried-channel transistor with an n-doped gate electrode cannot cope with steping of fine linewidth. With such structure, the gate electrode is built in a dual-gate type. To simplify fabrication steps, the gate electrode is subjected to doping simultaneous with formation of source and drain regions respectively for NMOS and PMOS structures. A self-aligned silicide technique (a salicide technique) also comes to broad utilization for raising drive power of the transistor, accompanied by finer steping and shallower junctions.
A device fabrication method, e.g., shown in FIGS. 26(a)-26(e), is conventionally known as a self-aligned silicide technique (a salicide-transistor technique) (K. Tsukamoto, T. Okamoto, M. Shimizu, T. Matsukawa and H. Harada: Extended Abstracts 16th Int. Conf. Solid State Devices & Materials, Kobe 1984 (Business Center for Academics Societies Japan, Tokyo, 1984) see p. 47). The method of FIGS. 26(a)-26(e) will be explained hereinbelow.
Referring to FIG. 26(a), a silicon semiconductor substrate 601 is formed thereon a field oxide layer 602, a gate oxide film 603, and a gate electrode of polysilicon 604 having side walls thereof covered with an insulation film. The gate electrode contains phosphorus as impurity ions diffused into polysilicon prior to patterning thereof. Then, as shown in FIG. 26(b), an oxide film 606 is deposited and a high concentration of impurity ions are implanted into areas for source and drain through the oxide film 606 with using photo-resist layer as a mask, not shown. As for impurity ions, arsenic ions are employed for an n-channel, while boron is used for a p-channel. Thereafter, a heat treatment for activation is performed, e.g., in a nitrogen ambient at 900.degree. C. for 30 minutes for formation of source and drain regions 607. The oxide film 606 is then removed from the surface of the source and rain regions 607 and the gate electrode 604, and thereafter a titanium film 608 is deposited by sputtering in an argon ambient, as shown in FIG. 26(c). then, a first rapid thermal anneal is performed in a nitrogen ambient at 675.degree. C. for approximately 20 seconds, as shown in FIG. 26(d) to react titanium with silicon in the surface layers of the source and drain regions 607 and the gate electrode 604, thereby forming a titanium silicide (TiSi.sub.2) of a C49-crystal structure which is stoichiometrically metastable. On this occasion, the surface of the titanium film 608 alters to a titanium nitride film 609. Etching is then made with using a solution mixture of sulfuric acid and hydrogen peroxide to remove unreacted titanium 608 and a titanium nitride film 609 formed by the first rapid thermal anneal, as shown in FIG. 26(e). Thereafter, a second rapid thermal anneal is performed in an nitrogen ambient at 800.degree. C. for approximately 20 seconds to transform the titanium silicide film 610 into a titanium silicide film (TiSi.sub.2) of a C54-crystal structure which is stoichiometrically stable.
There is also illustrated in FIGS. 28(a)-28(c) and FIGS. 29(d)-29(g) a conventional fabrication step utilizing a salicide technique for a dual-gate CMOS device. The step is briefly explained with reference to the drawings.
Referring to FIG. 28(a), a silicon semiconductor substrate 801 is first formed with a p-well 802 and an isolation layer 803. Thereafter, a gate dielectric film 804 is formed on the substrate, and a gate electrode 805 is formed to a thickness of, i.e., 2500 angstroms. Then, a thin insulation film 806 is deposited to implant .sup.31 P.sup.+ ions, thereby forming low-concentration (LDD) region 807, as shown in FIG. 28(b), followed by deposition of a thick insulation film 808 to a thickness of, e.g., 1000 angstroms, as shown in FIG. 28(c). The thick insulation film is then subjected to isotropic etching to form side wall spacers 809 on side walls of the gate electrode 805, as shown in FIG. 29(d). Subsequently, a thin insulation film 810 is deposited and then .sup.75 AS.sup.+ ions are implanted in a higher concentration, e.g., 3.times.10.sup.15 /cm.sup.2, than the .sup.31 P.sup.+ ions with an implant energy of 40 keV, for forming source and drain regions 811 and n.sup.+ -doping the gate electrode 805, as shown in FIG. 29(e). Then, annealing is done in a nitrogen ambient at 850.degree. C. for 10 minutes and treated by furnace annealing or RTA (Rapid thermal anneal) at 1000.degree. C. for 20 seconds, for activating n.sup.+ ions and restoring crystal defects in the LDD regions 808, the source and drain regions 811, and the gate electrode 805, as shown in FIG. 29(g). A refractory metal is then deposited by a technique such as sputtering and forming salicide 812 in a self-aligned manner through a heat treatment such as two-step RTA, providing a semiconductor device.
However, the conventional titanium silicide film forming step as above involves problems as given below.
(1) In a reaction system of Ti and Si, impurity ions are implanted through an oxide film, so that oxygen atoms, i.e., oxygen atoms undergoing knock-on upon implant of impurity ions, are inevitably mixed into a silicon semiconductor substrate (See FIG. 27). The mixing of oxygen atoms is particularly prominent when implanting heavy ions, resulting in silicidation reaction in a ternary element system of Ti, Si, and O.
(2) Silicidation by the ternary element system does not proceed necessary silicidation. Further, SiO.sub.2 is preferentially formed in grain boundaries of TiSi.sub.2, raising the sheet resist layerance and worsening the heat resist layerance of the titanium silicide film.
(3) Particularly, where silicidation is made in a linewidth finer than the grain size of TiSi.sub.2, the above problem (2) is prominent. That is, in silicidation in a linewidth finer than the grain size of TiSi.sub.2, transformation C49 into a C54-crystal structure from C49 is inapt to occur by a rapid thermal annealing (an RTA treatment) at 900.degree. C. or below, giving a high-resist layerance titanium silicide film. Conversely, where the RTA treatment is performed at a high temperature of 900.degree. C. or higher, the transformation of from C49 into the C54-crystal structure is apt to occur. However, there arises worsening of heat resist layerance and causing aggregation of TiSi.sub.2 as compared with a broader linewidth of titanium silicide films. Further, with a treatment at such temperature, aggregation begins to occur due to the effect of oxygen atoms even for titanium silicide films with a broader linewidth. There is therefore a problem that aggregation is certain to occur in a finer linewidth of titanium silicide films.
(4) In conventional silicidation, where a heat treatment is performed at such a temperature as to exceed 800.degree. C. after formation of a titanium silicide film, aggregation takes place in the titanium silicide film by the effect of oxygen atoms, resulting in diffusion of titanium into the silicon semiconductor substrate. This increases junction current leakage through the source and drain regions and lowers the reliability of the gate oxide film. As for silicidation for a linewidth of finer than the grain size of TiSi.sub.2, e.g., silicidation for a gate electrode, there is rise in the sheet resist layerance (resist layerivity of an interconnection) of a titanium silicide film to a level almost equivalent to that of an interconnection without being backed by a titanium silicide film.
(5) In the conventional CMOS forming method, a heat treatment (anneal) is simultaneously done for the n-channel and p-channel. However, the diffusion coefficient of boron in silicon for the p-channel is greater than that of arsenic for the n-channel. Consequently, source and drain regions on the p-channel side become deeper, prominently increasing the short-channel effect.
(6) Where conditions of a heat treatment (anneal) for activation of impurity ions are optimized to meet the p-channel side for suppressing the short-channel effect, crystal-defect restoration on the n-channel side is unsatisfactory, increasing junction current leakage in the n-channel side. Incidentally, an arsenic ion is heavier than an boron ion, effecting heavier damages in implanting.
(7) The junction depth of the source and drain regions is provided shallow by reducing implant energy for suppressing the transistor short-channel effect, lowering the temperature or briefing the time period of a heat treatment. However, a silicide formed is positioned closer to a silicide/silicon interface, the junction leakage current increases.
(8) The polysilicon gate electrode is thick and has low impurity concentration at the interface of the gate electrode and the gate dielectric film even if they are treated by low-energy implant with a low-temperature or brief-time heat treatment. As a result, the gate electrode when applied voltages causes depletion therein, leading to a short-channel effect or reduction of drive power.